A method for manufacturing SOI wafers has hitherto been disclosed in which, first, an oxide film is formed on at least one of two silicon wafers and a microbubble layer (trap layer) is formed at the interior of one of the silicon wafers by implanting hydrogen ions or rare-gas ions from the upper surface of the wafer. Next, the ion implanted surface of this wafer is brought into contact with the other wafer such that the oxide film is disposed therebetween, then heat treatment is applied; thereby splitting the first wafer into thin films at the microbubble layer as the cleavage plane (e.g., see Patent Document 1). In this SOI wafer manufacturing process, examples of techniques for removing the defect layer at the cleavage plane in the resulting SOI wafer include chemical mechanical polishing (CMP) method, sacrificial oxidation method involving heat treatment in an oxygen atmosphere to oxidize the near-surface region, and a gas-phase etching process known as plasma-assisted chemical etching (PACE). The PACE process is carried out with a pair of electrodes arranged on either side (above and below) the SOI wafer, a radio-frequency power supply that applies radio-frequency waves between the electrodes, and a cavity which is provided on one electrode opposite the SOI wafer and is capable of traveling freely over the SOI wafer. A plasma is localized and generated within the cavity, the plasma being used to etch the active layer. In order to etch the active layer using the PACE process, first the thickness distribution of the active layer on the SOI wafer is measured, then the velocity of travel by the cavity is controlled in accordance with this thickness distribution. In this way, the length of time during the active layer is exposed to the plasma is controlled, the crystal defect layer at the surface of the active layer can be removed while making the thickness of the active layer uniform.
However, in the SOI wafer manufacturing process described in Patent Document 1, the plasma generated within the cavity contains not only reactive radicals which do not cause any damage to the active layer, but also reactive ions which damage the active layer. Because these reactive ions are used as part of the etchant for etching the surface of the active layer, they end up causing damage to the active layer.
As for the CMP method and the sacrificial oxidation method, because both processes thin the entire surface at the same time, they cannot improve the in-plane uniformity in the thickness of the active layer. Also, the amount of thinning is not everywhere uniform in-plane, there being some variation in the initial in-plane thickness, which may have the opposite effect of degrading the in-plane uniformity.
Moreover, in the SOI wafer manufacturing process described in Patent Document 1, because the wafer shape is thinner at the periphery, bonding up to the vicinity of the wafer edge does not occur; thereby, an inactive region (1 to 2 mm in width) called the “terrace region” exists. The boundary line between the inactive region and the active region is often irregular rather than smooth. In particular, very small active regions which are isolated in the manner of islands or which jut out as peninsulas in the inactive region (terrace) have been a cause of particle generation.
Patent Document 1: Japanese Unexamined Patent Application, First Publication No. H11-102848 (Claim 1 and Paragraphs [0016], [0021] and [0030])